Investigations on mesa width design for 4H–SiC trench super junction Schottky diodes
Zhong Xue-Qian2, Wang Jue1, †, Wang Bao-Zhu2, Wang Heng-Yu2, Guo Qing2, Sheng Kuang2
College of Information and Electrical Engineering, Zhejiang University City College, Hangzhou 310015, China
College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China

 

† Corresponding author. E-mail: wangjue@zucc.edu.cn

Project supported by the National Key Research and Development Program of China (Grant No. 2016YFB0400502) and the National Natural Science Foundation of China (Grant Nos. U1766222 and 51777187).

Abstract

Mesa width (WM) is a key design parameter for SiC super junction (SJ) Schottky diodes (SBD) fabricated by the trench-etching-and-sidewall-implant method. This paper carries out a comprehensive investigation on how the mesa width design determines the device electrical performances and how it affects the degree of performance degradation induced by process variations. It is found that structures designed with narrower mesa widths can tolerant substantially larger charge imbalance for a given BV target, but have poor specific on-resistances. On the contrary, structures with wider mesa widths have superior on-state performances but their breakdown voltages are more sensitive to p-type doping variation. Medium WM structures (∼ 2 μm) exhibit stronger robustness against the process variation resulting from SiC deep trench etching. Devices with 2-μm mesa width were fabricated and electrically characterized. The fabricated SiC SJ SBDs have achieved a breakdown voltage of 1350 V with a specific on-resistance as low as 0.98 mΩ·cm2. The estimated specific drift on-resistance by subtracting substrate resistance is well below the theoretical one-dimensional unipolar limit of SiC material. The robustness of the voltage blocking capability against trench dimension variations has also been experimentally verified for the proposed SiC SJ SBD devices.

1. Introduction

Silicon carbide (SiC) unipolar power devices, such as power MOSFETs, JFETs, and SBDs, have been widely approved for their significant advantages in power electronics applications where improved efficiency, power density and higher temperature operation are required.[14] It is understood that for the SiC technology, unipolar devices are the preferred choices for the voltage range below 10 kV,[5] while bipolar devices such as IGBTs may be advantageous for applications higher than 15 kV. In the medium-to-high voltage range (3 kV to 10 kV) applications, emerging silicon carbide unipolar devices, such as SiC–MOSFETs, need to compete with mature Si bipolar devices, such as Si-IGBT. However SiC devices don’t exhibit distinct advantages in terms of the on-resistance/on-state voltage drop due to the lack of the conductivity modulation. In order to further reduce the specific on-resistance of SiC unipolar devices, methods that can break the one-dimensional specific on-resistance unipolar limit should be investigated. Super junction structures in 4H–SiC were proposed to break this limit and they provide exciting prospects for much better trade-off between the breakdown voltage (BV) and specific on-resistance (Ron,sp).[6,7]

Several experimental works have been carried out to develop SiC-based SJ power devices.[811] Unlike the multi-epitaxy-and-implant methods adopted In Refs. [8], [9], and [11] this group has successfully initiated a new technical route, namely trench-etching-and-sidewall-implant, to incorporate the SJ theory in SiC power devices. Based this novel method, the first functional SiC SJ device, a 1.35-kV SiC SJ Schottky diode has been reported by this group in 2016.[10]

In such trench-based SJ structures, mesa width plays a key role in determining the device electrical performances.[12,13] So it deserves a systematic observation and optimization study, especially for its first adoption in SiC-based SJ devices. To attain the above goals, this paper carries out the following work. In Section 2, the influences of mesa widths on device electrical characteristics are studied thoroughly via extensive numerical simulations and analysis. In Section 3, the impacts of mesa widths on device BV robustness against process variations are investigated in detail. In Section 4, the electrical characterization of the fabricated SiC SJ SBD devices is demonstrated and its robustness against key process variations is experimentally evaluated.

2. The effects of mesa widths on device electrical characteristics

The proposed trench super junction (SJ) Schottky diode (SBD) structure utilizes the trench-etching-and-sidewall-implant method. Figure 1 plots the basic cell structure. The main fabrication procedure is introduced as follows. The devices are fabricated on 12-μm-thick n-type epi-layer with a doping concentration of 7 × 1016 cm−3. SiC deep trenches are etched by inductive-coupled-plasma (ICP) techniques. Aluminum ions are then imported by multiple-step ion implantations and activated by high temperature annealing process. The p-type regions are designed to have box-shaped uniform doping profiles with a 0.5-μm depth at trench bottom and a 0.3-μm depth at each side of the trench. The SiC deep trenches are filled up by silicon oxide subsequently. Finally top and bottom nickel electrodes are deposited to finish the device fabrication.

Fig. 1. SiC SJ Schottky diode cell structure with basic dimensions.

Etching deep SiC trenches with high aspect ratio by inductive-coupled-plasma (ICP) is a key and challenging process step when fabricating the proposed SiC SJ SBD device. The proper trench depth demanded by 1.2-kV breakdown voltage target is 6 μm. Favorable trench profile with round bottom corners, like those in Fig. 2, has been achieved by fine-tuning the ICP etching recipe. Figure 2(a) is the SEM image of 6-μm-deep trench, which is the depth adopted in this work. This recipe has also been successfully utilized to etch deeper trenches such as the 8.1-μm-deep trenches shown in Fig. 2(b). The trenches still have smooth bottom corner and well-controlled cell pitch.

Fig. 2. Cross-sectional SEM image of the SiC deep trenches, (a) 6-μm deep and (b) 8.1-μm deep.

Device design optimization should be carried out to fulfill the benefits of such trench profiles. In the proposed SiC SJ SBD structures, most structure parameters are determined by the current process capability, for example, the trench sidewall angle (86 °C) and the trench opening width (WT, 3 μm). On the contrary, mesa width (WM in Fig. 1, the spacing between adjacent trenches) can be easily altered by photomask-level split design. Meanwhile, mesa width is a key structure parameter that significantly influences the device electrical performances. Therefore, the design optimization of mesa widths is not only necessary considering device performance improvement, but also realizable considering process capability. In this section, performances of SiC SJ SBDs with different mesa widths will be studied. Major structural parameters are plotted in Fig. 1 and five mesa widths varying from 1.2 μm to 2.8 μm are investigated. The electrical properties being investigated include the reverse blocking characteristics, charge imbalance window, forward conducting characteristics and Baliga’s figure of merit. 2D finite-element numerical simulations are implemented to aid the theoretical analysis. SILVACO Athena and Atlas are adopted as the simulator.

2.1. Reverse blocking characteristics

When evaluating the electrical performances of high voltage power devices, the breakdown voltage should be given high priority. Therefore, the voltage blocking capability of the proposed SiC SJ SBD structures with different mesa widths are studied first. For each mesa width, the p region doping concentration is swept over a reasonable range. Figure 3 plots the simulated breakdown voltage variation (above 1 kV) with the p-type region doping concentration for fieve different mesa widths. Each curve presents the similar trend of rising initially and declining afterwards. These correspond to the evolution of p-type dopants from under-compensation to over-compensation with respect to the n-type dopants.

Fig. 3. Simulated breakdown voltage versus p-type doping for varying mesa widths.

The impacts of charge compensation can be understood by electric field analysis. The structure with WM = 2 μm is taken for example and three typical charge compensation cases are investigated. Figure 4 (a) shows the 2D electric field distributions at voltage breakdown. Figure 4(b) extracts the electric field distribution along the border of p-type sidewall regions (cutline aa′) and the middle of n-type mesa region (cutline bb′). It should be noted that the simulated deep trench profile is adjusted accurately to fit the actual etching structure in experiment. The maximum breakdown voltages (BVmax) are achieved when the charges of opposite polarities are perfectly balanced. The corresponding p-type doping concentration is defined as Pmax. For the charge balanced situation (Case I), aa′ and bb′ distributions show a close-to-square region in the middle, thus best utilizing the 6-μm-thick SJ layer. It should be noted that, unlike conventional SJ structures,[7]the distributions in the middle regions are not completely flat and exhibit a curved shape instead. This is a unique property brought by the non-vertical 86 °C trench sidewall, whose effects resemble a linearly graded PN junction superimposing on the original distributions. With charge imbalances, an additional slope is superimposed onto the balanced distributions. When p doping concentration is below Pmax (Case II), the additional slope is negative, hence enhancing the peak electric field in y = 0 μm side. When p doping concentration is above Pmax (Case III), the additional slope is positive, hence enhancing the peak electric field in y = 6 μm side. In both Case II and III, the device breakdown voltage will degrade due to the non-uniform electric field distribution. The above analysis on the evolution of charge compensation applies to all the structures with different mesa widths.

Fig. 4. (color online) (a) The 2D electric field distribution at BV, and (b) the electric field distributions along the border of p-type sidewall region (aa′) and the middle of n-type mesa region (bb′) for structure with WM = 2 μm at three different charge compensation cases.

When observing the BVmax of structures with different mesa widths, it is found that BVmax drops after WM is greater than 2 μm, as shown in Fig. 3. This is due to the fact that the complete depletion of the SJ structure occurs at lower reverse voltage in structures with narrower WM. When the SJ structure works in the reverse blocking mode, a lateral depletion region is formed across the p-type stripe and n-type mesa.[7] Meanwhile two abrupt vertical junctions are formed near y = 0 μm side and y = 6 μm side, resulting in two electric field spikes at these two locations. Once the SJ structure is fully depleted by the lateral junctions (the reverse voltage at this point is defined as Vdel), with further increase in the reverse bias, Ex (the lateral component of the electric field) remains unchanged while Ey (the vertical component of the electric field) grows across the SJ region. The electric field spike formed before will be superimposed on Ey. Vdel of wider WM structures are obviously higher than narrower WM structures. Therefore both the Ex component and the Ey spikes are higher in wider WM structures. This can be confirmed by the 2D electric field distribution and cutline along two critical paths at BVmax for structures with three WM, as shown in Fig. 5. The maximum electric field increases with WM, which are 2.3, 2.4, and 2.7 MV/cm for 1.2 μm-, 2 μm-, and 2.8-μm WM structures, respectively. The local electric field crowding effects become more severe with increasing WM, resulting in an earlier voltage breakdown when WM is greater than 2 μm. When WM is smaller than 2 μm, the reverse blocking capability is slightly weakened due to the stronger electric field shielding effect at Schottky contact produced by the narrower mesa widths.

Fig. 5. 2D electric field and electric field distributions along critical paths at BVmax for structures with (a) WM = 1.2 μm, (b) WM = 2 μm, and (c) WM = 2.8 μm.
2.2. Charge imbalance window

The design window of p region doping concentration can be extracted from Fig. 3 and plotted in Fig. 6(a). The p-doping variation is defined as the difference between the actual p doping concentration (P) and the charge-balanced p region doping concentration where BVmax is achieved (Pmax). It can be observed that wider mesas are more sensitive to p doping variation than narrower mesas. For example, the doping variation window for 1.2-kV BV target is (−7.5 × 1016 cm−3, +6.5 × 1016 cm−3) for 1.2-μm WM structure and (−7 × 1016 cm−3, +2.5 × 1016 cm−3) for 2.8-μm WM structure. This phenomenon can be understood by considering Fig. 4 and Fig. 5 simultaneously. For the 2.8-μm WM structure, the electric field crowding effect at trench corners is already prominent at charge balance, as shown in Fig. 5(c). When an additional positive slope is superimposed due to the p-rich charge imbalance, the electric field strength near trench corner (point a′ in Fig. 5(c)) will increase rapidly, making the 2.8-μm WM structure vulnerable to p-doping over balance. Similar phenomenon occurs at point b for the p doping under balance case. When the charge imbalance percentage window (CI window, defined as (PPmax)/Pmax × 100%) is compared, the narrower mesa’s advantages become more overwhelming, as shown in Fig. 6(b), since Pmax of narrower mesa structures are obviously lower than that of wider structure. If the BV target is still 1.2 kV, the CI window for 1.2-μm WM structure is from −45% to +37.5% while the CI window for 2.8-m WM structure shrinks to the range from −21% to +7.6%. The CI window is particularly important for the SJ device design since in practice it is impossible to obtain a perfectly balanced charge profile, especially for the un-mature SiC SJ techniques. Therefore, superior CI window makes the narrower mesa widths attractive for the proposed SiC SJ SBD structure.

Fig. 6. Simulated breakdown voltage versus (a) p-type doping variation and (b) charge imbalance percentage for varying mesa widths
2.3. Forward conducting characteristics

The forward conducting characteristics are also simulated for the 5 different mesa widths with varying p-doping concentrations. Figure 7(a) shows the forward IV curves of each mesa width at their charge-balanced p-doping concentration (Pmax). The specific drift on-resistance (Rdri,sp) can be derived from the slope of the linear part of the curve where the diode has been fully turned on. Figure 7(b) summaries the extracted Rdri,sp for different mesa widths with varying p-doping concentrations. For mesa width of 1.2 μm, the Rdri,sp increases significantly with increasing p doping concentration. For mesa widths of 1.6 μm and 2 μm, the Rdri,sp presents a slight increase tendency. While for mesa widths of 2.4 μm and 2.8 μm, the Rdri,sp remains almost unchanged over the simulated p doping range. This is because the p-type region depletes part of the n-type mesa region, thus reducing the current conducting path width. This influence will gradually become insignificant with increasing mesa widths. In addition, it can be noted that the Rdri,sp drops almost exponentially with incremental mesa widths, since larger mesa width means higher effective current conducting area ratio over the total device area (for fixed trench dimensions). Considering the above reasons, the 1.2-μm WM structure is not a proper choice due to its high Rdri,sp and large Rdri,sp variation with p region doping concentration.

Fig. 7. (a) Simulated forward IV curves and (b) the extracted specific drift on-resistance versus p-type region doping for varying mesa widths.
2.4. Baliga’s figure of merits

Baliga’s figure of merits (BFOM = BV2/Rdri,sp) is a well-known parameter used to evaluate the trade-off between the breakdown voltage and the specific on-resistance of unipolar power semiconductor devices. BFOM of the investigated devices is depicted in Fig. 8. Clearly, wider mesa width results in a higher BFOM, due to their distinct advantages in Rdri,sp. For a fixed mesa width, the highest BFOM is achieved at its charge balanced p doping concentration (Pmax). In other words, the highest BFOM and the highest breakdown voltage occurs at the same p region doping concentration, where the opposite-polarity charges are perfectly balanced. BFOM of conventional SiC Junction Barrier SBD (JBS) devices are also calculated and plotted in Fig. 8 for comparison. The conventional SiC JBS structure is based on the same epitaxy structure and has same cell pitch and same junction spacing between adjacent p-type junctions with WM = 2-μm SJ SBD structure. It can been seen that BFOM of the proposed SiC SJ devices is almost 10 times higher than the conventional SiC JBS. BFOM of the proposed SiC SJ devices can be further improved by adopting trench structures with higher aspect ratio.

Fig. 8. (color online) Baliga’s figure of merits versus p-type region doping for varying mesa widths.

In summary, the maximum breakdown voltages (BVmax) present an initially rising and later on declining tendency with incremental mesa widths. The highest BVmax is achieved by the 2-μm WM structure. Narrower mesa widths own remarkably wider charge imbalance windows than wider mesa widths, which makes the narrower mesa widths (<2.4 μm) attractive for early experimental exploration of SiC SJ SBD structure. However the specific on-resistances increase with decreasing mesa widths and become unacceptably high when the mesa width is narrower than 2 μm. Therefore, if the charge imbalance can be controlled within a narrow window (e.g. ± 10%) by process techniques, wider mesa widths are preferred due to their superior Rdri,sp and BFOM. Overall, no specific mesa width can be recommended for an optimal design. It should be designed based on specific performance requirements and process capability. At the initial development stage of novel SiC SJ SBD devices, medium mesa widths (∼ 2 μm) can be adopted due to its balanced performances in all the evaluated electric characteristics.

3. The effects of mesa widths on acceptable fabrication variation windows

From the design considerations discussed in Section 2, it can be noted that the efficiency of SJ concept depends strongly on the balancing of charges of opposite polarities. In practice, however, it is impossible to obtain a perfectly balanced profile. Therefore, discussions on acceptable fabrication variation windows are essential for the development of SJ devices, especially for SiC-based SJ devices, where the fabrication process variations are expected at the initial experimental stage. Although favorable trench profile has been obtained by fine-tuning the etching recipe, trench opening width (WT) can still deviate from the target design due to the photolithography error, lateral etching of hard mask and other uncontrollable process errors. WT variation can have noticeable effects on the device electrical performances. The acceptable WT variation windows for 1.2-kV BV target differ for structures with different mesa width design. In this section, these effects will be studied in detail.

WT is designed to be 3 μm. Deviation from the designed WT will disturb the optimized charge balance design. The WT variation exerts two-fold effects on the SJ charge compensation. If WT is wider than designed, as illustrated in Fig. 9(b), the actual mesa width decreases due to the fixed cell pitch. This equals to an n-deficient charge imbalance situation. On the other hand, more Al ions will be implanted into the trench corner, causing an overlapped p region at trench corners. These two charge imbalance effects will add to each other and induce noticeable breakdown voltage degradations. Oppositely, WT values narrower than designed will lead to a WM widening-induced n-rich charge imbalance situation. Meanwhile the lower part of the vertical mesa will be shielded from scheduled implantation, resulting in a gap in the p region and thus a p-deficient charge imbalance, as shown in Fig. 9(c). These will also lead to reductions of breakdown voltage. Consequently, either WT widening or narrowing will cause SJ charge imbalance, resulting in deteriorations in device reverse blocking capability.

Fig. 9. (color online) Illustration of the trench opening width (WT) variations, (a) designed WT, (b) wider WT, and (c) narrower WT.

The BV degradation due to WT variation is quantitatively studied by numerical simulation. Firstly, a structure with WM = 2 μm and WT = 3 μm is studied. In simulation, the cell pitch (CP) is fixed at the sum of designed WM and WT values, which is 5 μm in this case. The implantation dose and angle remain the designed condition for target trench profile. This is what happens in actual experiments, since the cell pitch is determined by photomasks and the samples being implanted in one batch may include devices with varied WT. Four WT variation cases, including widening by 0.2 μm, 0.4 μm, narrowing by 0.2 μm, 0.4 μm are simulated. If the target (WT, WM) combination is expressed as (3 μm, 2 μm), the four WT variation cases can be expressed as (3.4 μm, 1.6 μm), (3.2 μm, 1.8 μm), (2.8 μm, 2.2 μm), and (2.6 μm, 2.4 μm), respectively. Figure 10(a) is the (WT = 3.4 μm, WM = 1.6 μm) case. The dopants crowding at trench bottom corners can be clearly observed from the simulated doping profile. This leads to a local electric field peak as high as 3.21 MV/cm at voltage breakdown. Combined with n-type dopants deficiency induced by the WM shrinkage, BV is degraded by 170 V. Figure 10(b) shows the (WT = 2.6 μm, WM = 2.4 μm) case. The Al dopants shielding effects can be clearly observed from the simulated doping profile. The excessive n-type doping concentration significantly lifts up the electric field peak at the Schottky contact surface, which reaches 2.89 MV/cm at voltage breakdown. The resultant BV is degraded by 270 V.

Fig. 10. (color online) The sidewall doping profile and electric field at breakdown for (a) WT = 3.4 μm and (b) WT = 2.6 μm, for the structure with target WM of 2 μm, where the cell pitch is fixed at 5 μm.

The BV degradation magnitude differs for structures with different mesa width design. Therefore, structures with four other mesa widths (1.2 μm, 1.6 μm, 2.4 μm, 2.8 μm, respectively) are studied following the same procedure introduced above. The simulation results are summarized in Fig. 11 (a), where the simulated BV with respect to ΔWT for five different mesa widths is plotted (ΔWT is defined as the difference value between the real WT and 3-μm target WT). When WT is narrowed (ΔWT < 0), the BV degradations show similar trends for all five mesa widths. BV drops around 100 V and 250 V when WT is narrowed by 0.2 μm and 0.4 μm, respectively. When WT is widened (ΔWT > 0), great discrepancy appears among structure with different mesa widths. BV s of structures with WM = 1.2 μm, 1.6 μm, and 2 μm present similar and slight dependency on WT variation. However, for structures with WM = 2.4 μm & 2.8 μm, BV drops sharply with wider WT. The SJ design completely loses its efficiency when WT is widened by 0.4 μm. This is because dopants crowding at trench bottom corners exert much severe negative impacts on these two structures, since they already suffer from high electric field at trench corners even at charge balance, as shown in Fig. 5(c). Their voltage blocking capabilities are very sensitive to the p doping concentration at trench corner regions. Figure 11(b) also gives the simulated Rdri,sp versus ΔWT for 5 different mesa widths. Rdri,sp becomes less sensitive to ΔWT with increasing mesa widths. This is because Rdri,sp changes due to the widening or shrinking of the effective current conducting path, while the influence of same amount ΔWT is less significant to wider mesa widths than narrower ones. For structures with WM = 1.2 μm & 1.6 μm, the WT widening may cause the p regions from adjacent sidewall to gradually pinch off. As a result, the forward currents saturate at relatively low current densities or even fail to be conducted, where Rdri,sp cannot be effectively extracted.

Fig. 11. (color online) Simulated (a) BV and (b) Rdri,sp versus trench opening width variation (ΔWT) for varying mesa widths.

In summary, structure designs with WM above 2 μm have poor BV robustness against WT variation while structures with WM below 2 μm has poor Rdri,sp robustness against WT variation. Medium WM structure designs (WM = 2 μm) possess wide acceptable WT variation windows for both conducting and blocking performance. For developing such a challenging device using novel process techniques, it is of primary importance to guarantee a feasible and controllable fabrication window. Based on the above considerations and accounting for its good electrical performances (including the highest BVmax, fine charge imbalance window as well as acceptable on-state performances), structure design with WM = 2 μm is selected for the fabrication and experimental demonstration of the proposed SiC SJ SBD devices.

4. Device fabrication and electrical characterizations

The proposed SiC SJ SBD devices were fabricated on initial wafers comprising a 4°-off 4H–SiC n-type substrate and a 12-μm-thick n-type epi-layer with a doping concentration of 7 × 1016 cm−3. After ICP trench etching, p-type aluminum ions were introduced into trench sidewalls by room temperature ion implantation with 20 °C tilt angle. Then the dopants were activated by high temperature annealing and the activation ratio was adjusted through annealing temperature. Extensive annealing experiments with annealing temperatures ranging from 1200 °C to 1400 °C were carried out and the reverse characteristics were measured subsequently. The sample annealed at 1350 °C attains obviously higher BV than other samples, where optimum charge balance has been obtained. The highest measured BV is 1350 V, achieving 92% of the simulated BVmax for the perfectly charge balanced SJ structure (1470 V). This result verifies that the charge balance target has been accurately hit in this experimental design. Therefore, the trench-etching-and-sidewall-implant method has been proved effective in realizing SJ concept in SiC power devices.

Next, the WT variation window accepted by 1.2-kV BV target is experimentally studied for the 2-μm WM structure based on the sample annealed at 1350 °C. As explained in Section 3, the actual WT could deviate from the 3-μm target design due to some uncontrollable process errors. In fact the non-target WT usually occurs at regions close to the edges of the sample where process instability is severe. Figure 12 shows the cross-sectional SEM images of devices with three typical WT values, the target WT (WT=3 μm), narrower WT (WT = 2.6 μm), and wider WT (WT = 3.4 μm).

Fig. 12. The SEM images of three typical WT situations, (a) target WT (WT = 3 μm), (b) narrower WT (WT = 2.6 μm), and (c) wider WT (WT = 3.4 μm). The cell pitches are fixed at 5 μm.

Devices of four WT variation cases, including widening by 0.2 μm, 0.4 μm, narrowing by 0.2 μm, 0.4 μm, were tested. Both the forward and reverse characteristics were measured and the IV curves are shown in Fig. 13. The relationship between the breakdown voltage and ΔWT is plotted in Fig. 14(a). Figure 14(a) also includes the simulated breakdown voltage for comparison. Devices with ± 0.2 μm–ΔWT realize breakdown voltage above 1.2 kV, proving the BV robustness against WT variation of the 2-μm WM structure. It should be mentioned that when WT deviates from the target design, the actual trench profile, including trench sidewall angle, bottom morphology and so on, will also change slightly but uncontrollably along with the WT variation, enlarging the difference between the real trench structure and target design. That may account for the discrepancy between the simulated and measured BVs. The specific on-resistances (Ron,sp) are extracted from the slope of the linear part of the on-state IV curves in Fig. 13 (b) and plotted in Fig. 14 (b). The simulated Rdri,sp is also included for comparison. The measured Ron,sp and simulated Rdri,sp present an almost identical increasing tendency with incremental WT. The difference between Ron,sp and Rdri,sp mainly comes from the substrate resistance. The 400-μm-thick SiC substrate contributes ∼ 0.5 mΩ ·cm2 to the total Ron,sp, which is calculated based on the Hall effect measured substrate resistivity. This value fits well with the data in Fig. 14(b). The measured 0.98 mΩ ·cm2 Ron,sp. for 1.35-kV SiC SJ SBD device is lower than any other state-of-the-art SiC power devices of similar voltage rating. With the development of SiC backside thinning techniques, the proposed SiC SJ SBD devices have the potential to realize specific on resistance substantially below the SiC unipolar limit.

Fig. 13. (color online) Experimental (a) reverse and (b) forward characteristics of the devices with different WT variations (ΔWT).
Fig. 14. (color online) The comparison of measured and simulated (a) breakdown voltage and (b) specific on-resistance for different trench opening width variations.
5. Conclusions

Mesa width is a key design parameter for the proposed SiC trench SJ SBD devices fabricated by the trench-etching-and-sidewall-implant method. The influences of mesa widths on device electrical characteristics are studied via extensive numerical simulations. It is found that structures designed with narrower mesa widths own remarkably wider charge imbalance window for a given BV target, but have poor specific on-resistances as well as BFOM. On the contrary, structures designed with larger mesa widths have superior on-state performances but their reverse blocking capabilities are vulnerable to the p-type doping variation. Regarding the acceptable fabrication variation windows, medium WM structures (WM = ∼ 2 μm) can maintain their voltage blocking capability and advantageous forward conducting performances over wider trench opening width ranges, thus having stronger robustness against the variation of SiC deep trench etching process.

Accounting for its combined features of excellent electrical performance and wide fabrication windows, structure with WM = 2 μm was fabricated and electrically characterized. The measured BV of the device with target trench opening width achieves 1350 V and the measured specific on resistance is 0.98 mΩ ·cm2. When the substrate resistance is calculated and subtracted from the measured value, the resultant specific on-resistance of the drift region (∼ 0.5 mΩ ·cm2) is well below the theoretical one-dimensional SiC unipolar limit. Meanwhile, the 1.2-kV BV target has been successfully accomplished within the WT variation window from −0.2 μm to +0.2 μm, thus experimentally verifying the robustness of the optimized SiC SJ SBD devices against key process variations. These experimental results make the trench-etching-and-sidewall-implant method attractive for the future development of SiC-based SJ devices towards higher voltage rating and more advanced structures.

Reference
[1] Bolotnikov A Losee P Permuy A Dunne G Kennerly S Rowden B Nasadoski J Harfman M Raju R Tao F Cioffi P Mueller F J Stevanovic 2015 Proc 2015 Ann. Appl. Power Electron. Conf. Exposit. March 15–19, 2015 2445
[2] Wang X D Deng X C Wang Y W Wang Y Wen Y Zhang B 2014 Chin. Phys. B 23 057203
[3] Chen S Z Sheng K 2014 Chin. Phys. B 23 077201
[4] Song Q W Tang X Y Yuan H Wang Y H Zhang Y M Guo H Jia R X Lv H L Zhang Y M Zhang Y M 2016 Chin. Phys. B 25 047102
[5] Cooper J A Tamaki T Walden G Sui Y Wang S R Wang X 2009 Proc. IEEE IEDM December 7–9, 2009 1
[6] Yu L C Sheng K 2006 Solid-Stat. Electron 50 1062
[7] Yu L C Sheng K 2008 IEEE Trans. Electron Dev. 55 1961
[8] Nishio J Ota C Hataketama T Shinohe T Kojima K Nishizawa S Ohashi H 2008 IEEE Trans. Electron Dev. 55 1954
[9] Kosugi R Sakuma Y Kojima K Itoh S Nagata A Tatsuo T Tanaka Y Okumura H 2014 Proc. 26th Int. Symp. Power Semicond. Devices ICs June 15–19, 2014 346
[10] Zhong X Q Wang B Z Sheng K 2016 Proc. 28th Int. Symp. Power Semicond. Devices ICs June 12–16, 2016 231
[11] Masuda T Kosugi R Hiyoshi T 2017 Mater. Sci. Forum 897 483
[12] Saito W Omura I Aida S Koduki S Izumisawa M Yoshioka H Okumura H Yamaguchi M Ogura T 2006 Proc. 18th Int. Symp. Power Semicond. Devices ICs June 4–8, 2006 18
[13] Sakakibara J Noda Y Shibata T Nogami S Yamaoka T Yamaguchi H 2008 Proc. 20th Int. Symp. Power Semicond. Devices ICs May, 18–22, 2008 299